<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="3.7.2" version="1.0">
  This file is intended to be loaded by Logisim-evolution v3.7.2(https://github.com/logisim-evolution/).

  <lib desc="#Wiring" name="0">
    <tool name="Pin">
      <a name="appearance" val="classic"/>
    </tool>
  </lib>
  <lib desc="#Gates" name="1"/>
  <lib desc="#Plexers" name="2"/>
  <lib desc="#Arithmetic" name="3"/>
  <lib desc="#Memory" name="4"/>
  <lib desc="#I/O" name="5"/>
  <lib desc="#TTL" name="6"/>
  <lib desc="#TCL" name="7"/>
  <lib desc="#Base" name="8"/>
  <lib desc="#BFH-Praktika" name="9"/>
  <lib desc="#Input/Output-Extra" name="10"/>
  <lib desc="#Soc" name="11"/>
  <main name="main"/>
  <options>
    <a name="gateUndefined" val="ignore"/>
    <a name="simlimit" val="1000"/>
    <a name="simrand" val="0"/>
  </options>
  <mappings>
    <tool lib="8" map="Button2" name="Menu Tool"/>
    <tool lib="8" map="Button3" name="Menu Tool"/>
    <tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
  </mappings>
  <toolbar>
    <tool lib="8" name="Poke Tool"/>
    <tool lib="8" name="Edit Tool"/>
    <tool lib="8" name="Wiring Tool"/>
    <tool lib="8" name="Text Tool"/>
    <sep/>
    <tool lib="0" name="Pin"/>
    <tool lib="0" name="Pin">
      <a name="facing" val="west"/>
      <a name="output" val="true"/>
    </tool>
    <sep/>
    <tool lib="1" name="NOT Gate"/>
    <tool lib="1" name="AND Gate"/>
    <tool lib="1" name="OR Gate"/>
    <tool lib="1" name="XOR Gate"/>
    <tool lib="1" name="NAND Gate"/>
    <tool lib="1" name="NOR Gate"/>
    <sep/>
    <tool lib="4" name="D Flip-Flop"/>
    <tool lib="4" name="Register"/>
  </toolbar>
  <circuit name="main">
    <a name="appearance" val="logisim_evolution"/>
    <a name="circuit" val="main"/>
    <a name="circuitnamedboxfixedsize" val="true"/>
    <a name="simulationFrequency" val="1.0"/>
    <comp lib="0" loc="(100,180)" name="Ground">
      <a name="facing" val="west"/>
    </comp>
    <comp lib="0" loc="(120,120)" name="Pin">
      <a name="appearance" val="NewPins"/>
      <a name="label" val="A"/>
    </comp>
    <comp lib="0" loc="(170,200)" name="Transistor">
      <a name="facing" val="south"/>
      <a name="selloc" val="bl"/>
      <a name="type" val="n"/>
    </comp>
    <comp lib="0" loc="(170,40)" name="Power"/>
    <comp lib="0" loc="(190,80)" name="Transistor"/>
    <comp lib="0" loc="(220,190)" name="Pin">
      <a name="appearance" val="NewPins"/>
      <a name="facing" val="west"/>
      <a name="label" val="NOT_A"/>
      <a name="output" val="true"/>
    </comp>
    <wire from="(100,180)" to="(100,190)"/>
    <wire from="(100,190)" to="(140,190)"/>
    <wire from="(120,120)" to="(130,120)"/>
    <wire from="(130,120)" to="(130,180)"/>
    <wire from="(130,180)" to="(150,180)"/>
    <wire from="(130,60)" to="(130,120)"/>
    <wire from="(130,60)" to="(170,60)"/>
    <wire from="(140,150)" to="(140,160)"/>
    <wire from="(140,160)" to="(140,190)"/>
    <wire from="(140,160)" to="(170,160)"/>
    <wire from="(140,50)" to="(140,80)"/>
    <wire from="(140,50)" to="(170,50)"/>
    <wire from="(140,80)" to="(150,80)"/>
    <wire from="(160,100)" to="(180,100)"/>
    <wire from="(170,200)" to="(180,200)"/>
    <wire from="(170,40)" to="(170,50)"/>
    <wire from="(180,100)" to="(180,190)"/>
    <wire from="(180,100)" to="(190,100)"/>
    <wire from="(180,190)" to="(180,200)"/>
    <wire from="(180,190)" to="(220,190)"/>
    <wire from="(190,80)" to="(190,100)"/>
  </circuit>
</project>
